VHDL Implementation and Coding of 4-bit Adder

To implement 4-bit adder we require the following Blocks

1. Half Adder
2.Full Adder

At first we have to implement the above two blocks then only we can implement the 4- bit adder. To know the code of the Half adder and Full Adder Click Here

This is the block diagram of the 4-Bit Adder.

The Code for 4-Bit adder is Shown Below

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-- Company: VHDL Language

-- Engineer: Manohar Mohanta

-- 

-- Create Date:    21:36:55 12/25/2016 

-- Design Name: 4-Bit Adder

-- Module Name:    Adder_4bit - Behavioral 

-- Project Name: Adder

-- Target Devices: 

-- Tool versions: 

-- Description: 

--

-- Dependencies: 

--

-- Revision: 

-- Revision 0.01 - File Created

-- Additional Comments: 

--

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity Adder_4bit is

    Port ( a : in  STD_LOGIC_VECTOR (3 downto 0);

           b : in  STD_LOGIC_VECTOR (3 downto 0);

           c : out  STD_LOGIC_VECTOR (3 downto 0);

           cout : out  STD_LOGIC);

end Adder_4bit;

architecture Behavioral of Adder_4bit is

Signal s: STD_LOGIC_VECTOR (2 downto 0);

begin

ha1:entity work.ha

port map( a =>a(0),b =>b(0),s=>c(0),c=>s(0));

fa1:entity work.fa

port map( a =>a(1),b =>b(1),cin=>s(0),s=>c(1),cout=>s(1));

fa2:entity work.fa

port map( a =>a(2),b =>b(2),cin=>s(1),s=>c(2),cout=>s(2));

fa3:entity work.fa

port map( a =>a(3),b =>b(3),cin=>s(2),s=>c(3),cout=>cout);

end Behavioral;

Code Explanation in the Below Video:-

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